Keyword ( s ) : Abstract : CACTI - IO Technical Report

 CACTI-IO Technical Report Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas HP Laboratories HPL-2013-79 IO; Interconnect; SERDES; PHY; Memory bus; DDR; LPDDR We describe CACTI-IO, an extension to CACTI that includes power, area and timing models for the IO and PHY of the off-chip memory interface for various server and mobile configurations. CACTI-IO enables quick design space exploration of the off-chip IO along with the DRAM and cache parameters. We describe the models added to CACTI-IO that help include the off-chip impact to the tradeoffs between memory capacity, bandwidth and power. This technical report also provides three standard configurations for the input parameters (DDR3, LPDDR2, and Wide-IO) and illustrates how the models can be modified for a custom configuration. The models are validated against SPICE simulations and show that we are within 0-15% error for different configurations. We also compare with measured results. External Posting Date: December 6, 2013 [Fulltext] Approved for External Publication Internal Posting Date: December 6, 2013 [Fulltext] Copyright 2013 Hewlett-Packard Development Company, L.P. CACTI-IO Technical Report Hewlett Packard Norman P. Jouppi3, Andrew B. Kahng1,2, Naveen Muralimanohar3 and Vaishnav Srinivas1 UC San Diego 1ECE and 2CSE Departments, La Jolla, CA. {abk, vaishnav}@ucsd.edu 3HP Labs, Palo Alto, CA. {norm.jouppi, naveen.muralimanohar}@hp.com